Sr. Manager, Physical Design Engineering, Annapurna LabsAmazon.com Inc.
Job Summary
Annapurna Labs, designs custom silicon powering AWSs cloud infrastructure. Custom SoCs live at the heart of Amazon ML servers including Inferentia and Trainium Systems delivering high-performance ML inference and training at cloud scale.
Were looking for a Senior Manager, Physical Design Engineering to build and lead a world-class Physical Design team delivering multi-billion-transistor ML accelerator SoCs on latest tech nodes.
Key job responsibilities
- Build, hire, and develop a physical design team of 10-15 engineers. Own headcount planning, performance management, career growth, and organizational scaling to support multiple concurrent tapeouts.
- Own the physical design strategy and execution roadmap across Inferentia, Trainium, and future products: implementation architecture, hierarchical methodology, PPA target-setting, and technology node adoption.
- Institutionalize continuous PPA improvement: benchmarking frameworks, regression tracking, design-quality dashboards, post-tapeout retrospectives, and structured improvement programs that compound across generations.
- Provide hands-on technical leadership on the hardest problems: multi-GHz timing closure, PDN architecture, high-speed I/O physical design, and 2.5D / 3D cross-die integration.
- Lead technology node enablement for 2nm and beyond: PDK evaluation, reference flow development, PPA pathfinding, and adoption recommendations.
- Define and deploy innovative RTL2GDS methodologies and CAD flows. Champion AI/ML-augmented design automation (RL-placement, ML-guided ECO, predictive analytics). Optimize cloud infrastructure for PD compute.
- Serve as part of senior technical interface with foundry partners and EDA vendors on tool roadmap, co-development, and technology co-optimization.
- Own tapeout execution: readiness reviews, foundry submittal, mask data coordination, and post-silicon yield learning. Drive cross-functional alignment with RTL, DFT, STA, Package, and Validation teams.
Were looking for a Senior Manager, Physical Design Engineering to build and lead a world-class Physical Design team delivering multi-billion-transistor ML accelerator SoCs on latest tech nodes.
Key job responsibilities
- Build, hire, and develop a physical design team of 10-15 engineers. Own headcount planning, performance management, career growth, and organizational scaling to support multiple concurrent tapeouts.
- Own the physical design strategy and execution roadmap across Inferentia, Trainium, and future products: implementation architecture, hierarchical methodology, PPA target-setting, and technology node adoption.
- Institutionalize continuous PPA improvement: benchmarking frameworks, regression tracking, design-quality dashboards, post-tapeout retrospectives, and structured improvement programs that compound across generations.
- Provide hands-on technical leadership on the hardest problems: multi-GHz timing closure, PDN architecture, high-speed I/O physical design, and 2.5D / 3D cross-die integration.
- Lead technology node enablement for 2nm and beyond: PDK evaluation, reference flow development, PPA pathfinding, and adoption recommendations.
- Define and deploy innovative RTL2GDS methodologies and CAD flows. Champion AI/ML-augmented design automation (RL-placement, ML-guided ECO, predictive analytics). Optimize cloud infrastructure for PD compute.
- Serve as part of senior technical interface with foundry partners and EDA vendors on tool roadmap, co-development, and technology co-optimization.
- Own tapeout execution: readiness reviews, foundry submittal, mask data coordination, and post-silicon yield learning. Drive cross-functional alignment with RTL, DFT, STA, Package, and Validation teams.