Senior Engineer, SoC HALAmazon.com Inc.
Job Summary
Annapurna Labs builds the custom silicon at the heart of AWS machine learning servers, and we are hiring a senior engineer to own the architecture of the Hardware Abstraction Layer (HAL) that brings these chips to life. If you love working where hardware meets software, writing the code that boots, configures, and debugs some of the largest custom silicon in the world, this is your team.
As a Software Development Engineer III on the SoC HAL team, you will set the software architecture for the driver stack across multiple hardware blocks and chip generations, partner directly with the hardware designers who build the silicon, and raise the engineering bar for a small, fast-moving team inside a large organization. No machine learning background is required (you will pick up ML concepts from colleagues if you want to). This role can be based in Cupertino, CA or Austin, TX.
Key job responsibilities
- Own the design and end-to-end implementation of the HAL/driver software architecture for new chips, including the abstractions, interfaces, and patterns the rest of the team builds against.
- Apply hardware/software co-design principles, partnering early with RTL designers and design verification engineers to shape the manageability and debuggability of the silicon before tape-out.
- Deliver and maintain HAL blocks across the stack (for example PCIe, DDR / HBM memory, DMA, system fabric, interrupt controllers, and boot / firmware), and support prior chips with feature additions and bug fixes.
- Set the standard for how the team tests and continuously deploys the software stack to internal customers, including pre-silicon and hardware-in-the-loop flows.
- Make durable, well-reasoned technical tradeoffs and drive cross-team decisions that span hardware, firmware, and higher-layer system software.
- Mentor and coach other engineers, lead design and code reviews, and act as a technical lead for architecture and engineering best practices.
A day in the life
A typical day moves between writing and reviewing C++ for the HAL, working through a hardware interface question with an RTL or design verification engineer, and shaping the architecture for a block still being designed. You might debug a failure spanning software and silicon, then define the abstractions a new chip will need. Your stakeholders are the hardware design, verification, firmware, and system-software teams; your customers are the internal software teams that rely on the HAL to boot, configure, and debug the chip. Problems range from talking to brand-new hardware to scaling the stack across chip generations.
About the team
Annapurna Labs designs and deploys some of the largest custom silicon in the world, including the Trainium and Inferentia machine learning accelerators. Our SoC HAL team builds the low-level software that boots, configures, and manages these chips, sitting between the hardware and the system software that runs the server. We are a small team that works closely with hardware, holds a high engineering bar, and gives engineers real ownership to shape the architecture they build. Split between Cupertino, CA and Austin, TX with no site preference, we value mentorship, clear written design, and software that outlasts any single chip.
As a Software Development Engineer III on the SoC HAL team, you will set the software architecture for the driver stack across multiple hardware blocks and chip generations, partner directly with the hardware designers who build the silicon, and raise the engineering bar for a small, fast-moving team inside a large organization. No machine learning background is required (you will pick up ML concepts from colleagues if you want to). This role can be based in Cupertino, CA or Austin, TX.
Key job responsibilities
- Own the design and end-to-end implementation of the HAL/driver software architecture for new chips, including the abstractions, interfaces, and patterns the rest of the team builds against.
- Apply hardware/software co-design principles, partnering early with RTL designers and design verification engineers to shape the manageability and debuggability of the silicon before tape-out.
- Deliver and maintain HAL blocks across the stack (for example PCIe, DDR / HBM memory, DMA, system fabric, interrupt controllers, and boot / firmware), and support prior chips with feature additions and bug fixes.
- Set the standard for how the team tests and continuously deploys the software stack to internal customers, including pre-silicon and hardware-in-the-loop flows.
- Make durable, well-reasoned technical tradeoffs and drive cross-team decisions that span hardware, firmware, and higher-layer system software.
- Mentor and coach other engineers, lead design and code reviews, and act as a technical lead for architecture and engineering best practices.
A day in the life
A typical day moves between writing and reviewing C++ for the HAL, working through a hardware interface question with an RTL or design verification engineer, and shaping the architecture for a block still being designed. You might debug a failure spanning software and silicon, then define the abstractions a new chip will need. Your stakeholders are the hardware design, verification, firmware, and system-software teams; your customers are the internal software teams that rely on the HAL to boot, configure, and debug the chip. Problems range from talking to brand-new hardware to scaling the stack across chip generations.
About the team
Annapurna Labs designs and deploys some of the largest custom silicon in the world, including the Trainium and Inferentia machine learning accelerators. Our SoC HAL team builds the low-level software that boots, configures, and manages these chips, sitting between the hardware and the system software that runs the server. We are a small team that works closely with hardware, holds a high engineering bar, and gives engineers real ownership to shape the architecture they build. Split between Cupertino, CA and Austin, TX with no site preference, we value mentorship, clear written design, and software that outlasts any single chip.