Missile Systems (MS) is seeking technical leaders that are passionate about the design and application of configurable logic technologies to the development of world-class defense solutions and secure protection of the solutions. MS is seeking a Senior Engineers to help expand the capabilities, quality, and proficiency of FPGA and ASIC design as it pertains to design security within MS and the company as a whole. This position requires an established depth of expertise in secure processing subsystems. The position also requires established depth in FPGAs, ASICs, and systems on chips (SOCs) design, and a complimentary breadth of experience in adjacent disciplines: electronics design, software design, systems engineering, and signal processing.
The candidate shall have demonstrated leadership and visionary thinking throughout the full design cycle of implementing system security layers based on ASIC and FPGA technologies that are deployed on advanced modular electronic systems. The full design cycle activities includes but is not limited to assessing capabilities of the system, mission planning, defining required security layers for the system, performing trade studies and architecting layers of the security boundaries, designing layers and modules of the security applications, verifying the security layers and validating the security layers with the appropriate DOD organizations, and supporting the security layers into production.
The Senior Engineer will be expected to support multiple programs in the proposal, architecture and design phases to insure the optimal application of configurable logic technologies, coordinating efforts across design disciplines, and organizational boundaries. This coordination will include the oversight of those designs through formal and informal reviews, the application of model-based engineering, and process improvements. The Senior Engineer will be a focal point for ASIC and FPGA security design expertise, often relied upon by programs to provide specific complex solutions and analysis, as well as having a broad responsibility to help define technology road maps, propose IRAD projects and set functional priorities to realize those road maps.
In addition to advancing the state of the art in FPGA and ASIC security design and processes, the Senior Engineer is expected to distribute their expertise through formal and informal mentoring, reviews, educational presentations, and wiki articles.
Please Note: This position can be a Sr. Electrical Engineer II or Principal Electrical Engineer based on the candidate's qualifications as they relate to the skills, experience and responsibility requirements for the position.
U.S. Citizenship required
- Experience in the assessment of secure approaches and methodologies including :
- Secure Software Boot
- Crypto suites
- System and Device Key Management
- Software methodologies that utilize secure capabilities
- Entropy sources
- Secure Mission Planning
- Experience in Developing requirements and trade studies for security layers using fore mentioned approaches within electronics subsystems
- Experience with architecting, modeling, designing, implementing, testing and validating secure applications on electronics sub-systems including applying tools, developing workflows and models, and planning
- Experience with Production lifecycle support of secure systems
- Experience with Verification and Validation of methodologies and approaches
- In depth of knowledge in FPGA and ASIC technologies, which includes: Vendor tools and technology from Xilinx, Altera, & Microsemi, Software/Hardware languages (C, C++, VHDL, UVM & System Verilog, Python), comprehensive knowledge of FPGA/ASIC design flow, including CM, Simulation, Synthesis, P&R, script languages, verification, and integration.
- In depth of knowledge in the implementation of modern verification environments that include the use of constrained-random stimulus, functional coverage, code coverage, coverage collectors, scoreboards, monitors, creation of models to use through requirements to verification, and verification plans which determine the appropriate level of verification applications
- Experience with emulation and prototyping techniques.
Required Education and Experience:
- Prior experience working with DOD organizations starting with formulation through validation of secure systems
- Experience developing new and novel concepts leading to the capture and execution of technology maturation and development programs, transitioning into real products and deployed systems
- Experience with all aspects of embedded system design and development processes
- Have a record of Patents, Publications, and/or Technical Presentations to industry
- Active Secret Clearance/SCI
- Knowledge of ASIC design flow and process
- Comprehensive knowledge of CL design tools, including CM, Simulation, Synthesis, P&R, script languages, etc.
- Strong written and verbal communication skills, including experience communicating and presenting to all levels of the organization including senior level executives and external customers.
- The ability to train and mentor others through various means including informal mentoring, reviews, presentations, publications and training.
This position requires the successful issuance, transfer or maintenance of any clearances and/or accesses necessary for the position. Non-US citizens may not be eligible to obtain a security clearance. The Defense Industrial Security Clearance Office (DISCO), an agency of the Department of Defense, handles and adjudicates the security clearance process. Security clearance factors include, but are not limited to, allegiance to the US, foreign influence, foreign preference, criminal conduct, security violations and drug involvement. Additional detail regarding security clearance factors can be obtained by accessing the DISCO website at
- Bachelor of Science in Computer or Electrical Engineering with a minimum of 6 years of relevant experience.
Raytheon is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, age, color, religion, creed, sex, sexual orientation, gender identity, national origin, disability, or protected Veteran status.